This relates generally to processor-based devices that transmit information to be displayed on a display over a physical layer interface.
Conventionally, displays receive the information they are to display from a display transmit engine, such as a processor-based device. The transmission of the information occurs over physical layer interface. The physical layer interface may include data lanes and control channels.
An interface pursuant to the DisplayPort standard version 1.2 includes a main link with four lanes and a side channel, called an auxiliary channel, for link and device management. A hot plug detect interface may also be provided.
Generally, devices that attempt to manage the power consumption of physical layer interfaces, such as the DisplayPort physical layer, control the link as a whole, either allowing data to be transmitted or not. Also, the power can be cut off to the processor-based device. Alternatively, the PHY may be disabled and put in the clock gated mode, but even then it continues to dissipate significant power, which multiplies depending on how long the system stays in this state.
The reason why the PHY cannot be put in an extremely low power mode, such as the power gated mode, is because the PHY is an analog circuit and requires a long latency time to wake up and condition itself to get ready for data transmission. Since the long latency impacts the user experience, generally a PHY is not allowed to go into a power gated state in any mode where low wake up latency is a requirement.